AMD announced a definitive agreement to acquire Toronto-based Taalas on 6 August. The technology etches model weights into a chip's metal layers, eliminating the DRAM read of the full weight set per generated token. The natural objection — permanent silicon is a bet a model is finished — is partly answered by a design flow that customizes two metal layers of roughly a hundred and turns a chip at TSMC in about two months. That still isn't as fast as the industry ships models, which is why this suits small high-volume models rather than frontier ones.
AMD announced a definitive agreement on 6 August to acquire Taalas, a Toronto startup founded in 2023 by former Tenstorrent and AMD architects. Terms were not disclosed. The technology is unusual enough to have carried the coverage on its own: Taalas etches a model's weights permanently into the wiring of a chip, so that running the model no longer requires reading it out of memory. The obvious objection writes itself — models change every few weeks and silicon is forever. The interesting part is that Taalas has an answer to that objection, and the answer is more revealing than the speed number.
When a GPU generates a token, it does not merely compute. It reads the model's weights out of high-bandwidth memory and streams them through the arithmetic units. Then it does it again for the next token. For a large model the arithmetic is comparatively cheap and the memory traffic is not, which is why inference performance tracks memory bandwidth more closely than it tracks raw FLOPS, and why accelerator vendors have spent years buying every HBM stack they can source. This is the memory wall, and it is the reason a chip can look fast on paper and generate tokens slowly in practice.
Taalas removes the read rather than accelerating it. If the weights are physically encoded in the transistors and metal layers of the die, there is no weight fetch, because there is nothing to fetch — the values are the circuit. It is an elegant answer to a real problem, and the elegance is not in dispute.
The company's first test chip, HC1, is a TSMC N6 die that encodes all of Llama 3.1 8B into what Taalas calls a mask ROM recall fabric, spanning 53 billion transistors. Taalas quotes it at roughly 17,000 tokens per second per user at around 200 watts. Those figures come from Taalas's own testing of Taalas's own chip, relayed through trade coverage, and no independent benchmark has been published. Take them as a vendor claim about a test part, not a product specification.
Even discounted, the direction is clear. Seventeen thousand tokens per second per user is not a marginal improvement on a GPU serving the same model; it is a different regime, and it makes previously impractical things practical — speculative decoding at scale, agent loops that run dozens of sequential model calls inside a single user-facing interaction, and real-time applications where a hundred milliseconds of generation latency is the whole product.
Permanent silicon is, on its face, a bet that a model is finished. That is a strange bet to make in this industry. DeepSeek recently shipped a materially better model on unchanged architecture and unchanged parameter count, purely by redoing post-training. Meta released a new agentic model last week distilled from a base model that is itself only weeks old. The industry's release cadence is measured in weeks. A mask ROM is not.
But the design flow addresses this more directly than the framing suggests. Taalas customizes two metal layers out of roughly a hundred per model, and reports turning a model-specific chip at TSMC in about two months. That is the number worth holding onto. It means the base die is shared and only a thin customization layer is model-specific, which is how the economics work at all — you are not taping out a new chip from scratch for every checkpoint.
Two months is fast for silicon and slow for models. That gap, not the tokens-per-second figure, defines which workloads this technology suits.
So the question is not whether etched inference is viable — a two-month turn makes it viable for something. The question is which models are stable enough to be worth two months and a mask set. The honest answer is: probably not frontier models, which are superseded on roughly that timescale and whose value lies in being current. It is the small, boring, high-volume ones — the classifier that routes every support ticket, the embedding model behind a search box, the 8B assistant sitting inside a product and called ten million times a day. Those models get frozen for months or years, often deliberately, because changing them means requalifying everything downstream. Their operators care about cost per token and latency, and not at all about being on the newest checkpoint.
That is a genuinely different market from the one GPU vendors have been competing in, and it explains the acquisition better than the speed number does. It is also a smaller market than the announcement implies, which is worth saying plainly.
The comparison being drawn in coverage is to Nvidia and Groq, and it needs a correction. That transaction was announced on 24 December 2025 at roughly $20 billion, and it was structured as an asset purchase and non-exclusive licensing arrangement rather than a conventional acquisition — a distinction some coverage of the AMD deal has flattened. Dated properly, AMD's move comes a little over seven months later.
The pattern is still the point. Inside eight months, both major GPU vendors have paid to acquire inference-specific silicon expertise rather than building it internally or assuming their general-purpose accelerators would absorb the workload. That is a concession, and a fairly candid one: the assumption that the chip which trains the model is also the right chip to serve it is no longer being treated as safe. Training is a bandwidth-and-scale problem with relatively few customers. Inference is a latency-and-cost problem with a vast number of them, and the two have been drifting apart for a while.
AMD says it will integrate the technology into its accelerator roadmap alongside Instinct GPUs, the Helios rack-scale platform, EPYC CPUs and the ROCm stack — which is the company's stated plan, not a shipped product. The deal is expected to close in Q4 2026 and has not closed yet.
Nothing, for a while. There is no Taalas-derived AMD product on the market, the deal has not closed, and integration into a shipping roadmap is measured in years rather than quarters. Anyone reading this as near-term downward pressure on API prices is reading too fast.
The medium-term effect, if it arrives, is a widening gap between two kinds of inference. Frontier-model calls stay expensive because they run on general-purpose accelerators and the models keep changing. Commodity inference on frozen small models gets substantially cheaper because it moves onto fixed-function silicon. Those prices have moved together so far, mostly because they ran on the same hardware. There is now a credible reason for them to separate — and a reason for anyone architecting a system to think carefully about which of their calls genuinely need a frontier model.
Performance and transistor figures are Taalas's own published test-chip results as relayed through trade coverage; no independent benchmarks exist. Deal terms were not disclosed and the transaction has not closed.
Functionally, it keeps serving the model it was built for and nothing else — the weights are the circuit, so they cannot be updated in place. Taalas mitigates this at the manufacturing end rather than the field end: only two metal layers out of roughly a hundred are model-specific, and the company reports turning a new model-specific chip at TSMC in about two months. So the answer is that you replace the part rather than reprogram it, and the economics only work for models whose useful life comfortably exceeds that cycle.
DrafterDaily reads chip deals for the assumption underneath them — what a vendor is conceding, not what it is claiming.
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